1. Field of the Invention
The present invention relates to integrated circuit memory devices including a delay locked loop (DLL) circuit.
2. Description of the Related Art
A concern with integrated circuit memory devices is power consumption. One component of an integrated circuit memory device responsible for a significant amount of power consumption is the delay locked loop circuit. Delayed locked loop (DLL) circuits are used, for example, in synchronous dynamic random access memory (SDRAM). This type of DRAM operates in synchronization with an externally applied clock signal. Specifically, the DLL circuit generates an internal clock signal used for synchronization from the externally supplied clock signal.
SDRAM and DRAM in general are types of volatile memory devices—meaning that, over time the charges, which represent logic values, that are stored by capacitors in the memory device leak away. This leaking is caused by parasitic capacitance in the memory device. Consequently, such volatile memory devices perform a refresh operation wherein the charges are refreshed. During the refresh operation, the internal clock signal generated by the DLL circuit is not needed. As a result, a prior art technique for reducing power consumption involves ceasing the supply of power to the DLL circuit during the refresh mode and resetting the DLL circuit.
A DLL circuit includes a phase detector and a variable delay unit. The phase detector detects the phase difference between the external clock signal and a fed back version of the internal clock signal generated by the DLL circuit. The variable delay unit delays the external clock signal by an amount that varies based on the detected phase difference to produce the internal clock signal. When powering up, the DLL circuit typically takes more than 200 clock cycles to lock onto the external clock signal. This means the DLL circuit takes more than 200 clock cycles for the variable delay unit to substantially stabilize the amount of delay in generating the internal clock signal. Because of this, the delay established by the variable delay unit is often referred to as the locking information. When the DLL circuit is reset, such as during the refresh operation, the locking information is lost. More specifically, resetting the DLL circuit causes the variable delay unit to reset to a preprogrammed delay. Consequently, after each refresh operation, more than 200 clock cycles must pass before the DLL circuit locks onto the external clock signal and begins generating an appropriate internal clock signal. As such it takes more than 200 clock cycles after each refresh operation before the memory device can begin further operation.
Frequent refresh operations may, therefore, degrade the performance of the semiconductor memory device. Also, the power consumed during the more than 200 clock cycle lock operation may off-set any reductions in power consumption achieved by ceasing the supply of power to the DLL circuit and resetting the DLL circuit during the refresh operation.